[Home] Checking ISP registers


Read, set, and check ISP registers

Use a raw capture from the CCDC to put the data into memory, bypassing the preview, resizer, and other ISP auxilaries.


This document is just a note-taking place right now. Don't expect useful information below.



Outline of ISP documentation in SPRUF98G

Since TI didn't have the decency to create HTML documentation, nor to sort the documentation by topic, here's a bite-size breakdown of ISP-related information in spruf98g.pdf:




Outline of SPRS507F - OMAP3530/25 Applications Processor

Relating to the Linux Kernel

12.5.3 Programming the Timing CTRL Module

12.5.4 Programming the CCDC

Table 12-50. CCDC Required Configuration Parameters Input-Mode Selection

SYNC mode:

NOTE: Timing Generator and Frame Settings

The polarities of the cam_hs, cam_vs, and cam_fld signals are controlled by the CCDC_SYN_MODE[3] HDPOL, CCDC_SYN_MODE[2] VDPOL, and CCDC_SYN_MODE[4] FLDPOL bit fields. The polarities can be positive or negative.

The pixel data is presented on cam_d one pixel for every cam_pclk rising edge or falling edge. It is controlled with the ISP_CTRL[4] PAR_CLK_POL bit.

The CCDC_SYN_MODE[7] FLDMODE bit fields set the image-sensor type to progressive or interlaced mode. When the sensor is interlaced, the CCDC_SYN_MODE[15] FLDSTAT status bit indicates whether the current frame is odd or even.

The polarity of the cam_d signal can also be controlled with the CCDC_SYN_MODE[6] DATAPOL bit field.

The polarity can be normal mode or ones complement mode.

Furthermore, the directions of the cam_fld and cam_hs/cam_vs signals are controlled by the CCDC_SYN_MODE[1] FLDOUT and CCDC_SYN_MODE[0] VDHDOUT bits. If CCDC_SYN_MODE[0] VDHDOUT is set as an output, the CCDC_PIX_LINES register controls the length of the cam_hs and cam_vs signals.


Figure 12-107 shows the HS/VS sync pulse output timings. Image-Signal Processing

12.5.9 Programming the Central-Resource SBL


Table 12-88. ISP_CTRL

12.6.5 Camera ISP_CCDC Registers

Table 12-193. CCDC_SYN_MODE


cam_pclk must start before sending cam_d and start cam_vs and cam_hs

RAW can be processed via IVA2.2 in software

SYNC mode: In this mode, the cam_hs and cam_vs signals use dedicated wires. Synchronization signals are provided by either the sensor or the camera ISP. This mode works with 8-, 10-, 11-, and 12-bit data. It supports both progressive and interlaced image-sensor modules. SYNC CTRL Module

The SYNC CTRL module receives the pixel-clock signal from the image sensor (PCLK). The module can be slave or master of the horizontal and vertical synchronization signals (HS and VS) and of the field-identification signal (FIELD).

The HS, VS, and FLD signals can be set as inputs or outputs. The polarity of the HS, VS, and FLD signals can be set as positive or negative. If the HS, VS, and FLD signals are output, the signal length can be set.

For RAW data:

Conversion Area Select Parameters

When the data formatter is enabled, HS/VS signals are still generated as output (CCDC_SYN_MODE [16] VDHDEN = 0x1). The settings for these output signals are in the following fields:

NOTE: These four registers are not used when HS/VS signals are input signals (CCDC_SYN_MODE [16] VDHDEN = 0x0).

NOTE: The settings reflect those for the sensor readout frame, not the resultant reformatted frame. Registers CCDC_FMT_HORZ and CCDC_FMT_VERT control the interpretation of the input data frame when the data formatter is enabled.

Registers CCDC_HORZ_INFO, CCDC_VERT_START, and CCDC_VERT_LINES control the interpretation of the input data frame in normal mode (when the data formatter is not enabled).

Resizer Physical Address 0x480B D000

spruf98g.pdf - page 1636 -

Table 12-423. RSZ_HFILT10


Address Offset 0x0000 0028 Physical Address 0x480B D028


On page 1458 there is a complete table with all the registers and values for those registers that need to be initialized for the CCDC to function.

Via the kernel

It seems that isp_interface_config is the struct which is used to set the isp registers in the kernel

A Note to TI

Next time your Table of Contents is 163 pages, consider putting it up in o googleable format, maybe? Or, better yet, don't do silly things - like create 34-hundred page manuals! Perhaps better to break it down by use-case or topic? Each major section in another manual unto itself?

Updated at 2010-08-03
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